1. Field of the Invention
The present general inventive concept relates to semiconductor memory devices, and more particularly, to synchronous memory devices having a block-dedicated programmable latency register.
2. Description of the Related Art
FIG. 1 is a timing diagram illustrating a read operation of a semiconductor memory device (SDRAM). In FIG. 1, CLK refers to a clock signal, COMMAND in this example refers to a read command, ADDRESS refers to a signal providing instructions to access a column address, and DATA OUTPUT illustrates the output of the memory device at any particular time. Latency generally refers to the time between the start and the completion of an event. In synchronous DRAMs, latency is usually counted by the number of clocks taken for a particular even. As illustrated in FIG. 1, CAS (column address strobe) Latency refers to the time between the start and the completion of a read operation in a column address of a memory space within an SDRAM, or the latency by the number of clocks from the READ command (together with the Column Address command) to the first data output. Stated differently, CAS Latency refers to a parameter used by the SDRAM to synchronize the output data obtained as a result of a READ request (command) with a particular edge of the system clock (CLK). The “Burst Length” refers to the number of consecutive output data as a result of a READ command (in FIG. 1 the Burst Length=4). As illustrated in FIG. 1, when the READ command and the Column Address command are provided, the consecutive number of clocks before the start of the data output is the CAS Latency, which in this example is a CAS Latency=3.
FIG. 2 illustrates an intrinsic speed parameter of a DRAM data path, or a number of required operations for the data access time of a DRAM from when a column ADDRESS command is entered. As illustrated in FIG. 2, tAA is the intrinsic speed parameter of a DRAM data path, which limits fundamentally the number of CL required to obtain proper data output as a result of the READ command (the data access time by the number of clocks). Thus, CL cannot exceed the value of tAA (tAA<CL×tCK). For example, if tCK and tAA is 5 ns (200 Mhz) and 15 ns respectively, the minimum value of CL is 4. With a tAA of 15 ns and tCK of 2.5 ns (400 Mhz), the minimum CL is 7. Since the column address request occurs at the column select line (CSL), the value of tAA depends on the distance from the CSL to the Dout Driver.
The CL value is commonly programmed using a Mode Register Set (MRS) command. A mode register is used to define the specific mode of operation of an SDRAM. In other words, the mode register stores the data for controlling the various operation modes of DDR SDRAM. FIG. 3 illustrates a mode register and the mode register set (MRS). The mode register programs CAS Latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not defined, and therefore the mode register must be written after an external mode register set (EMRS) setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS. CAS. WE and BA0 (the DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0-A11 (A12) in the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, and the addressing mode uses A3, CAS latency (read latency from column address) uses A4-A6. A7 is used for test mode and A8 is used for DLL reset. A7 must be set to low for normal MRS operation. The CAS Latency table illustrates to specific codes for various burst lengths, addressing modes and CAS latencies.
As described above and illustrated in FIG. 3, it is clear that CL is commonly programmed using an MRS command. FIG. 4 illustrates how the MRS command is used to set a CL value to 2, for example, when A4 is set to logic 0, A5 is set to logic 1, and A6 is set to logic 0 (see table FIG. 3). As a result, the CL (CAS Latency) is programmed to be a value of 2 by the mode register.
FIG. 5A illustrates a memory device of a conventional SDRAM device, and how it is divided into Banks, i.e., Bank A, Bank B, Bank C and Bank D. In turn, each of the Banks is divided into a plurality of memory blocks (i.e., block 0-block n), as illustrated in FIG. 5B. Moreover, each of the memory blocks can include a plurality of memory cells. Each of the blocks within a bank can be accessed by row and column addresses, provided as logic codes. For example, FIG. 6A illustrates a bank of a memory device, which is divided into many memory blocks. The memory blocks in the bank illustrated in FIG. 6A can be selected to be accessed for reading the data stored therein by activating a part of row addresses and column addresses using binary logic, as illustrated in FIGS. 6B and 6C.
In view of the above discussion of operations of an SDRAM, a conventional synchronous memory device and its operations will be discussed below.
Conventional synchronous memory devices are allowed to have only one CAS latency (CL) value, which is programmed using an MRS command, as described supra. In other words, the first one of the burst read data is designed to be output in the same number of clocks when the READ command is entered, regardless of the spatial distance of the designated memory block (or cell) from a data output circuitry block including data output buffers, which receives the data being read. The data being read is commonly chosen to be read by the appropriate column and row address provided by the ADDRESS with read command (see FIG. 1). The burst data is output to the data output circuitry block including the data output buffers. However, the data path to the data output circuitry block from the cells in a near-side block (i.e., a closest block to the output circuitry block) can be expected to have a shorter access time than a far-side block (i.e., a farthest block from the output circuitry block). FIG. 7 illustrates a memory bank including a plurality of blocks (Blocks 0-n), and how the blocks are decoded with respect to a row decoder and a column decoder. As illustrated in FIG. 7, block_0 is a near-side block with respect to output circuits and pads (i.e., the output circuitry block), while block_n is a far-side block with respect to the output circuits and pads. The difference in this distance can be represented by the following equation: ΔtAA=tAA far−tAA near, where ΔtAA is the difference of tAA (data access time) between near-side and far-side memory blocks.
If only one CL value is permitted to be used, as is the case in conventional synchronous memory devices, the tAA of the memory device is decided by the data access time of the farthest block of the memory device (i.e., the far-side block). In other words, since the CL value refers to the time it takes between the start and the completion of a read operation in an SDRAM (see FIG. 1), the CL value must be set in consideration of the longest data access time (data received from the far-side block). Thus, if only one value of CL is permitted for a memory device, as in conventional SDRAMs, the data of the near-side block often must wait for a period of time longer than necessary to be accessed, although this data is in fact ready to be accessed at an earlier time than that of the far-side block. In addition to the above stated drawbacks of the conventional SDRAMs, some additional drawbacks that result using conventional SDRAMs are listed below.
As market demand increases for faster memory devices with larger memory density, it is with certainty that memory sizes will continue to become larger while the operating clock cycle time tCK will continue to be reduced. As the memory sizes become larger, the difference between the far-side and near-side block (ΔtAA) will also become larger, and ΔtAA will become larger than the clock cycle time tCK. As a result, as memory devices continue to grow while continuing to have only one CL value, it is certain that total memory performance of the memory devises will experience critical losses. For example, as tCK becomes smaller and smaller, the ΔtAA will become larger than one tCK, and if memories have only one CL while their determination of CL value continues to be based on the access time from a far-side block, the data from a near-side block will have to be delayed by more than one tCK to meet the CL requirement.